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SM8750AV
NIPPON PRECISION CIRCUITS INC.
Data Jitter Measurement IC
OVERVIEW
The SM8750AV is a data jitter measurement CMOS LSI for adaptive control.
FEATURES
s
PINOUT
Top view
s
s
s s s s s
RDCLK and DATA signal phase difference to voltage converter (75mV/ns (typ) coefficient) RDCLK duty auto-adjust function (rising edge reference) DATA signal delay auto-adjust function (independently adjusted on rising and falling edges) Offset auto-calibration function 3-wire serial interface mode control Sleep function Single 5V supply 16-pin VSOP
START DATA CALMON RDCLK LIMIT SENB SCLK SDATA
1
16
VDD TVOUT VREF2 RCP RDUTY RDATAF RDATAR
875 0 A V
APPLICATIONS
s
8
9
GND
s
Optical disc equipment * CD-R * CD-RW * DVD-RAM * Others Control/governing equipment
PACKAGE DIMENSIONS
Unit: mm
ORDERING INFORMATION
D e vice S M 8 7 5 0 AV P ackag e 16-pin V S O P
+ 0. 0.15 - 0. 10 05
4.4 0.2
6.4 0.2
1.15 0.1
0.10 0.05
0.275typ 5.1 0.2
0 to 10
0.65
0.10 + 0.1 0.22 - 0.05 0.12 M
NIPPON PRECISION CIRCUITS--1
0.5 0.2
SM8750AV
BLOCK DIAGRAM
DATA START VDD TVOUT VDD 47k CALMON Phase comparator Charge pump output buffer (phase difference to voltage converter) VREF2 RCP 33k RDUTY 22k RDCLK LIMIT SENB to each block Serial interface Delay correction RDATAF 39k
Automatic regulation controller
Duty correction
SCLK SDATA GND
RDATAR 39k
PIN DESCRIPTION
Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name S TA R T D ATA CALMON RDCLK LIMIT SENB SCLK S D ATA GND R D ATA R R D ATA F RDUTY RCP VREF2 T VO U T VDD I/O I I O I I I I I/O - O O O O I O - Description Measurement star t control. Phase difference to voltage conversion starts on the falling edge. Tw o-valued signal input Internal calibration state signal monitor output. N-channel open drain. Active when calibrated. PLL clock input T VOUT output voltage-limit control voltage input Serial interface: enable signal input Serial interface: clock signal input Serial interface: data signal input/acknowledge signal output. N-channel open drain. Ground D ATA rising edge: delay adjust circuit reference-current setting resistor connection D ATA falling edge: delay adjust circuit reference-current setting resistor connection RDCLK duty adjust circuit reference-current setting resistor connection Phase difference to voltage converter coefficient reference-current setting resistor connection 2V reference voltage input Phase difference to voltage converter output 5V supply
NIPPON PRECISION CIRCUITS--2
SM8750AV
SPECIFICATIONS
Absolute Maximum Ratings
GND = 0V
P arameter Supply voltage range Input voltage range Storage temperature range Pow er dissipation Symbol VDD V IN T stg PD Rating -0.5 to 7.0 -0.5 to V D D + 0.5 -40 to 125 250 Unit V V C mW
Recommended Operating Conditions
GND = 0V
P arameter Supply voltage (specifications guaranteed) Supply voltage (operation guaranteed) Reference voltage input Operating temperature range Symbol VDD VDD VREF2 T opr Rating 4.75 to 5.25 4.5 to 5.5 1.89 to 2.11 0 to 70 Unit V V V C
DC Electrical Characteristics
VDD = 5V 5%, GND = 0V, Ta = 0 to 70C
Rating P arameter Symbol ID D 1 ID D 2 HIGH-level logic input voltage 2 L O W -level logic input HIGH-level logic input L O W -level logic input voltage 2 current 2 current 2 V IH V IL IIH IIL VOL IR E F V IN = V D D V IN = G N D IO L = 10mA VRFE2 = 2V Condition min Current consumption 1 Nor mal operating mode Sleep mode - - 2.4 - - -3 - - typ 9.0 0.5 - - - - - 50 max 13.0 mA 0.7 - 0.6 3 - 1.0 100 V V A A V A Unit
S D ATA, CALMON logic output voltage VREF2 input current
1. 39k resistor connected betwe e n R DATA R a n d G N D 39k resistor connected betwe e n R DATA F a n d G N D 22k resistor connected betwe e n R D U T Y a n d G N D 33k resistor connected betwe e n R C P a n d G N D 60MHz RDCLK input frequency 7.5MHz DATA input frequency 200kHz STA R T input frequency 0ns DATA and RDCLK phase difference Serial interface not operating. 2. Pins STA R T, DATA , R D C L K , S E N B, SCLK, SDATA.
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SM8750AV
Phase Difference to Voltage Converter Characteristics
VDD = 5V 5%, GND = 0V, Ta = 0 to 70C
Rating P arameter F C G = L OW RDCLK input frequency FCG = HIGH Phase difference to voltage converter coefficient 1 Phase difference to voltage converter coefficient 2 Phase difference to voltage converter coefficient 3 C o n verter coefficient relative accuracy C o n verter coefficient relative accuracy Output offset voltage C o n verter voltage settling time C o n verter voltage reset time Output load regulation HIGH-level output voltage range L O W -level output voltage range Output voltage droop S TA R T-DATA setup time 3 S TA R T signal rising edge to DATA signal edge Nor mal operation, FCG = L O W C o n verter coefficient measurement mode, FCG = LOW Nor mal operation, FCG = H I G H C o n verter coefficient measurement mode, FCG = HIGH See note.1 See note.2 - 50 25 25 12.5 - - - - - - +0.15 0.8 - 1T 29.19 75 37.5 37.5 18.75 - - - - - - - - - - 35 100 50 mV/ns 50 25 5 5 25 0.75 3 20 +0.45 - 1 - mV/ns % % mV s s mV V V mV/s ns mV/ns Condition min - typ 58.38 max 70 MHz Unit
After VREF2 reference calibration Time from measurement object DATA edge to final set value 0.5% Time from STA R T signal rising edge to final reset value 1mV IL = 0.5mA LIMIT pin voltage reference
1. {[(converter coefficient 2) x 2 / (converter coefficient 1)] - 1} x 100 2. {[(converter coefficient 3) x 2 / (converter coefficient 2)] - 1} x 100 3. T = RDCLK cycle time
Auto-adjust Characteristics
VDD = 5V 5%, GND = 0V, Ta = 0 to 70C
Rating P arameter M a x i m u m DATA edge delay adjust range Minimu m DATA edge delay adjust range M a x i m um RDCLK pulsewidth adjust range F C G = L OW Minimum RDCLK pulsewidth adjust range M a x i m um RDCLK pulsewidth adjust range FCG = HIGH Minimum RDCLK pulsewidth adjust range A uto-adjustment time R C P voltage HIGH-level RDATA R / R DATAF voltage L O W -level RDATA R / R DATAF voltage HIGH-level RDUTY voltage L O W -level RDUTY voltage After CS = HIGH, until settling C o n verter coefficients set Minimu m DATA delay M a x i m u m DATA delay Minimum RDCLK pulsewidth M a x i m um RDCLK pulsewidth - - - - - - - 4 5 1 1.92 0.69 1.88 0.24 - 8 - - - - - ns ms V V V V V - - 3 28 - - ns ns Condition min - - - typ 29 12.5 15 max - - - ns ns ns Unit
NIPPON PRECISION CIRCUITS--4
SM8750AV
Serial Interface Characteristics
Rating P arameter SCLK pulse cycle time SCLK HIGH-level pulsewidth S C L K L OW -level pulsewidth SENB setup time SENB hold time S D ATA setup time S D ATA hold time A CK setup A CK hold time 1 Symbol min tc y S C K tw h S C K tw l S C K ts S E N th S E N ts S DA th S D A ts AC K th AC K ti n S E N 100 40 40 20 40 15 15 0 - 100 typ - - - - - - - - - - max - - - - - - - 20 50 - ns ns ns ns ns ns ns ns ns ns Unit
time 1
SENB inter val
1. S D ATA output signal (ACK) acknowledge output (N-channel open drain), receive data is valid, LOW -level output, 15pF SDATA load capacitance.
tinSEN SENB tsSEN tcySCK SCLOCK tsSDA SDATA Controller SDATA port bit0 LSB thSDA bit1 bit15 MSB tsACK thACK twhSCK twlSCK thSEN
ACK High impedance
NIPPON PRECISION CIRCUITS--5
SM8750AV
FUNCTIONAL DESCRIPTION
Serial Interface
The SM8750AV has a dedicated serial interface port over which data can be written and the various operating modes can be controlled. The port address and
Table 1. Port address and bit configuration
Bit nu m b e r 15 (msb) 14 13 12 Data TEST1 TEST0 CSDIS CS SP POLAR GMES FCG x LOW HIGH 11 10 9 8 7 6 5 4 Address HIGH HIGH HIGH HIGH x 3 2 1 0 (lsb)
bit configuration are shown in table 1, and the data bits are described in table 2.
x: Don't care.
Table 2. Data bit description
Bit TEST[1:0] CSDIS CS SP POLAR GMES FCG Test mode setting A uto-adjust disable A uto-adjust start Sleep mode settings D ATA edge settings for phase measurement Polarity setting for converter coefficient measurement C o n verter coefficient measurement mode setting RDCLK pulsewidth auto-adjust mode Phase difference to voltage converter coefficient switching Description L OW:LOW LOW LOW LOW LOW LOW LOW Default (normal operation) (enabled) (wait) (normal operation) (falling edge) (1T discharge) (normal operation) (minimum pulsewidth) (maximum converter coefficient)
Table 3. GMES and POLAR operating modes
GMES LOW LOW HIGH HIGH POLAR LOW HIGH LOW HIGH Operating mode D ATA signal falling edge and RDCLK rising edge phase difference conversion D ATA signal rising edge and RDCLK rising edge phase difference conversion Output converter voltage for phase difference equivalent to -0.5T Output converter voltage for phase difference equivalent to +0.5T
Serial data comprising 16 bits is input with the LSB first. Valid data is read in on the 16th rising edge of the SCLK input. On the next SCLK falling edge, the SDATA N-channel open drain is turned ON and SDATA goes LOW, performing the function of an acknowledge signal. If 15 or less SCLK rising edge pulses occur during the interval when SENB is HIGH, the data received
up to the point when SENB goes LOW is ignored and the internal port data is not updated. If 17 or more SCLK rising edge pulses occur, the received data is latched in the internal port on the 16th rising edge and the acknowledge signal is output on the next falling edge. The acknowledge signal is held constant until SENB goes LOW again.
NIPPON PRECISION CIRCUITS--6
SM8750AV
Phase Difference to Voltage Converter
The phase difference to voltage converter circuit takes the converts the phase difference between the RDCLK rising edge and the DATA signal to a voltage. When START goes LOW, the phase difference between the first active DATA signal edge, where the active edge polarity is determined by the serial interface bit POLAR, and the next RDCLK rising edge is converted to a voltage signal. The converted voltage signal is output on TVOUT while START is LOW, and is reset to the VREF2 reference level when START goes HIGH again. The START signal must go LOW for a minimum interval of 1 RDCLK cycle before any DATA signal edge to be converted, regardless of the number of DATA signal edges. If the START interval is shorter than 1 cycle, there is a possibility that the next edge might be misinterpreted as the conversion object.
START RDCLK
Phase difference START-DATA set up time
DATA
Internal charge signal
Internal discharge signal
Conversion voltage VREF2 Reset VREF2
TVOUT output
Figure 1. Converter operation timing (POLAR = LOW, DATA leading phase)
START RDCLK
Phase difference START-DATA set up time
DATA
Internal charge signal
Internal discharge signal
VREF2 Reset Conversion voltage VREF2
TVOUT output
Figure 2. Converter operation timing (POLAR = LOW, DATA lagging phase)
NIPPON PRECISION CIRCUITS--7
SM8750AV
Converter Coefficient Measurement Mode
When the serial interface bit GMES is set HIGH, converter coefficient measurement mode is invoked. In this mode, a voltage equivalent to a phase difference of 0.5T, determined by the POLAR input bit, is output on TVOUT. Internally, the difference in pulsewidth between the charge/discharge signals is 1T, where the charge pump circuit capacitance is double the capacitance during normal operation in order to generate outputs equivalent to phase differences of 0.5T.
START RDCLK
Internal charge signal
Internal discharge signal
Reset VREF2 Conversion voltage (corresponds to -0.5T) VREF2
TVOUT output
Figure 3. Converter coefficient measurement mode timing (POLAR = LOW)
START RDCLK
Internal charge signal
Internal discharge signal
Conversion voltage (corresponds to +0.5T) Reset VREF2
TVOUT output
VREF2
Figure 4. Converter coefficient measurement mode timing (POLAR = HIGH)
NIPPON PRECISION CIRCUITS--8
SM8750AV
Auto-adjust Function
When the serial interface bit CS is set HIGH, the auto-adjust function starts and operates on the objects in the sequence described below. In the autoadjust sequence cycle, the RDCLK pulsewidth and DATA delay are set to approximately the center of the adjustment range. 1. Charge pump circuit and output buffer offset cancellation An identical 0.5T signal is added to the charge/discharge signals and the output on TVOUT is calibrated to an output voltage of VREF2. 2. RDCLK pulsewidth Signals equivalent to the RDCLK HIGH-level pulsewidth and LOW-level pulsewidth are added to the internal charge/discharge signals, and the RDCLK pulsewidths are adjusted to recover a TVOUT output voltage of VREF2. 3. DATA rising edge delay The phase difference between the RDCLK rising edge and DATA rising edge is converted to a voltage, and the RDCLK rising edge delay is adjusted to recover a TVOUT output voltage of VREF2. 4. DATA falling edge delay The phase difference between the RDCLK rising edge and DATA falling edge is converted to a voltage, and the RDCLK rising edge delay is adjusted to recover a TVOUT output voltage of VREF2. The CALMON calibration monitor output is high impedance during the auto-adjust sequence interval. When auto-adjustment is completed, the CALMON N-channel open drain turns ON and CALMON goes LOW, and the CS bit is cleared to LOW. When the serial interface bit CSDIS is set HIGH, the auto-adjustment result is disabled, and the external inputs on RDCLK and DATA are input to the phase comparator without adjustment. If CS and CSDIS are both simultaneously set HIGH, the auto-adjust sequence still takes place but that the result is disabled as soon as the sequence is completed. When power is switched ON, the auto-adjust sequence is enabled, and the adjusted values are approximately in the center of the corresponding adjustment range.
Sleep Mode
When the serial interface bit SP is set HIGH, sleep mode is invoked. In this mode, all circuits other than the power-ON detection circuit and serial interface circuit are shutdown to reduce current consumption. When operation transfers from sleep mode to normal operating mode, the auto-adjust settings from the most recent auto-adjust cycle are restored.
Power-ON Reset
When power is switched ON, a built-in power-ON reset circuit sets all serial interface bit settings to LOW (factory preset default), and the auto-adjust circuit settings are set to the middle of the corresponding adjustment range.
Test Mode
When the serial interface bit TEST1 or TEST0 is set HIGH, a test mode is invoked. In these modes, the phase comparator input signals and internal
Table 4. Test modes
TEST1 LOW LOW HIGH TEST0 LOW HIGH LOW Nor mal operation Internal charge signal Phase comparator RDCLK signal CALMON Nor mal operation Internal discharge signal Phase comparator DATA signal T VO U T
charge/discharge signals are output on CALMON and TVOUT.
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SM8750AV
NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility fo r the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with expor t controls on the distribution or dissemination of the products. Customers shall not expor t, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2-chome Koto-ku, Tokyo 135-8430, Japan Telephone: 03-3642-6661 Facsimile: 03-3642-6698
NC9916AE 2000.07
NIPPON PRECISION CIRCUITS INC.
NIPPON PRECISION CIRCUITS--10

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